osbl_authosbl_hashosbl_sahara_ifcrc.cAssertion byte_ptr != NULL failedAssertion buf_ptr != NULL failedInvalid SMEM buffer size requested for memory %d.Invalid SMEM memory type, %d, requested.smem.cInvalid memory type %dOut of shared memory have %d requested %d for %dThe smem allocation table is too smallCan't initialize heap infoSMEM layout mismatch for %d %x != %xsdioc_init_proc.cAssertion "Unsupported SDIOC device" == NULL failedAssertion dr == DAL_SUCCESS failedCopy to smem failed!Sources SMEM init failed!clkrgm_mpss_boot.cspinlock.cInvalid argument to spin_lockInvalid argument to spin_unlockclkrgm_sources.cReconfiguring local active PLL: %d[clk_regime_is_source_enabled] Source out of range: %d[clk_regime_is_source_client] Client out of range: %d[clk_regime_source_request] Client out of range: %dCannot reconfigure shared PLL: %d, votes=0x%xResource %d is exclusive, used by %x (c=%d)Clock %d released (usage=%d, ext=%d)Clock %d requested (usage=%d, ext=%d)Client %d released resource %d (clients=%x)Client %d requested resource %d (clients=%x)clkrgm_rm.cUsage count already zero, clock=%dInvalid client/resource: c=%d, r=%dInvalid resource: r=%dNeed code changes to support more than 64 clientsUnsupported Regime EMDH Unsupported Regime PMDH Cannot switch adsp clk, not owned by processor!Unsupported Regime MI2S CODEC RX on this Target!Unsupported Regime MI2S CODEC TX on this Target!Unsupported Regime vdc on this Target!Unsupported Regime ecodec on this Target!Unsupported Regime GPclkrgm_msm.cUnsupported Regime VFE new_src: %dUnsupported Regime SDC1 speed: %dUnsupported Regime UART1 speed: %dNot the Regime Owner UART1 speed: %dUnsupported Regime SDC2 speed: %dUnsupported Regime UART2 speed: %dNot the Regime Owner UART2 speed: %dUnsupported Regime SDC3 speed: %dUnsupported Regime UART3 speed: %dNot the Regime Owner UART3 speed: %dUnsupported Regime SDC4 speed: %dUnsupported Regime UART1DM speed: %dInvalid VFE source: %dUnsupported GP source: %dUnsupported QDSP6 regime: %dUnsupported Regime vdc perf: %dUnsupported sdac cfg: %dUnsupported Regime sdac cfg: %dUnsupported sdc cfg: %dUnsupported ecodec cfg: %dUnsupported Regime ecodec cfg: %dUnsupported icodec_rx cfg: %dUnsupported Regime icodec_rx cfg: %dUnsupported icodec_tx cfg: %dUnsupported Regime icodec_tx cfg: %dInvalid GP config: %dUnsupported clk: %d freq: %d Match: %dUnsupported clk: %d freq: %d match: %d[clk_regime_msm_off] Unsupported clock: %d[clk_regime_msm_on] Unsupported clock: %d[clk_regime_msm_reset] Unsupported clock: %d[clk_regime_msm_reset_assert] Unsupported clock: %d[clk_regime_msm_reset_deassert] Unsupported clock: %d[clk_regime_msm_sel_clk_inv] Unsupported clock: %dClock divider request for unsupported clock: %d[clk_regime_msm_is_enabled] Invalid clock: %d[clk_regime_msm_is_supported] Invalid clock: %d[clk_regime_msm_enable] Invalid clock: %d[clk_regime_msm_disable] Invalid clock: %d[clk_regime_msm_off] Invalid clock: %d[clk_regime_msm_on] Invalid clock: %d[clk_regime_msm_is_on] Invalid clock: %d[clk_regime_msm_reset] Invalid clock: %d[clk_regime_msm_on] Processor not owner of clock: %dUnsupported ADSP clk: %dUnsupported Regime MI2S CODEC RX new_clk: %dUnsupported Regime MI2S CODEC TX new_clk: %dUnsupported QDSP6 performance level: %dUnsupported Regime MDP_LCDC freq: %dUnsupported Regime Camera new_freq: %d[clk_regime_msm_get_perf_level_freq_khz] Unsupported param: %d %dUnable to find regime %d in sync list of %dNULL source for clk %dInvalid UARTDM config: regime=%d, cfg=%dInvalid UART config: clk=%d, cfg=%dInvalid UART: clk=%dCannot switch %d clk, not supportedClock %d mux not supportedPMIC: GPIO ENABLE set to HIGH PMIC: End pm_vreg_set_level_TI_TPS62651_external_smps() call with Range ERROR PMIC: End pm_vreg_set_level_TI_TPS62651_external_smps() call with SUCCESS PMIC: GPIO ENABLE set to LOW PMIC: Start pm_vreg_control_TI_TPS62651_external_smps() call cmd = %d PMIC: Start pm_vreg_set_level_TI_TPS62651_external_smps() call level = %d, NACK status = %d PMIC: pm_DalI2C_Read() reg = %x, val = %x, result = %d PMIC: End pm_vreg_control_TI_TPS62651_external_smps() call PMIC: Before pm_set_vsel_high_operating_mode()pm_vreg_external_smps_i.cPMIC: setting VSEL low, threshokd = %d, status = %dPMIC: setting VSEL high, threshold = %d, status = %dPMIC: pm_DalI2C_Write() reg = %x, val = %x, result = %dPMIC: End pm_vreg_set_level_TI_TPS62651_external_smps() call with ERROR. Will use GPIO nowPMIC: Could not set SMPS high operating mode. I2C write error: %xclkrgm_msm_bridge.cInvalid bridge: %dInvalid bridge request: %dBridge control for %d tied to clockUnable to switch fabric clock!clkrgm_fabric.cUnsupported FABRIC perf level: fabric_clk=%dclkrgm_sdram.cUnsupported SDRAM perf level: sdram_clk=%dclkrgm_msm_rm.cInvalid resource or clk: r=%d, clk=%dMDM1000QST1000MDM2000MDM3000QST1100MDM6200MSM7200MDM8200MDM9200QST1500MSM7500QST1600MDM6600MSM7600MDM9600QST1700MSM7800MDM8900MDM6210MDM6610MDM8220MSM7230MSM7630ESC6240QSC6240QSD8250QSD8550QSD8650QSD8850APQ8060MSM6260MSM8260MSM8660ESC6270QSC6270MSM6280ESM6290MSM6290MSM7225-1MSM7625-1MSM7227-1MSM7627-1MSM7201MSM7601MSM7625-2MSM7627-2QSD8672QST1005QST1105ESM7205MDM6215MDM6615ESM7225MSM7225MSM7525MSM7625ESM6235MSM6245APQ8055QSC6155MSM6255MSM8255MSM8655QSC6165QSC6175QSC6185QSC6285QSC6195ESC6295QSC6295QSC6695ESM7206ESM6246MSM6246ESM7227MSM7227MSM7627MSM7200AMDM8200AMSM7500AQSD8250AQSD8650AMSM7201AESM7205AMSM6255AESM7206AUNKNOWNADMH00INTCTL0TXR0ADMH01FPB1SDC1CLK_CTL_SH1SPI1INTCTL1SDIO1TLMMGPIO1TXR1GEN2AXI_NX1ADMH02A2FPB2SDC2CLK_CTL_SH2SSBI2SPI2INTCTL2SDIO2EBI2CS2UART2GEN2AXI_NX2ADMH03FPB3SDC3CLK_CTL_SH3INTCTL3CRYPTO3UART3SDC4INTCTL4SDC5INTCTL5INTCTL6INTCTL7CRADFABPERPH_WEBAHB2AHBQDSP6FWSS_PUBQDSP6SWSS_PUBCWBCGPS_GACCGNSS_ADCQLICTOP_FABRICUSB2_HSICXMEMCQDSP6FWSS_SIRCQDSP6SWSS_SIRCMPSS_AHB_MISCNTCRFDEBI2NDO_RX_FEDAYTONA_PIPESPARESIC_NON_SECURETSIFMPSS_MUTEX_REGQDSP6FW_L2TCM_CFGQDSP6SW_L2TCM_CFGTGTLMMGPIO1SHPEIMPSS_ARM9_MTIWCDMA_DEMBACKSDC1_DMLSDC2_DMLSDC3_DMLSDC4_DMLSDC5_DMLMEM_POOLSEC_CTRLMPSS_SEC_INTCTLCHIP_PRI_INTCTLCLK_CTLSDC1_BAMSDIO1_BAMA2_BAMSDC2_BAMSDIO2_BAMSDC3_BAMSDC4_BAMSDC5_BAMUSB2_HSIC_BAMUSB1_HS_BAMIRAMPPSS_CODE_RAMPPSS_BUF_RAMUART1DMNAV_DMHDEMMODEMMDSPMEMDAYTONA_PMEMQDSP6FWSS_IMQDSP6SWSS_IMBPMA9_MPMEBI2XMMPSS_TIMERS_MICROMPSS_TIMERS_SLPEVPEBI2CRDECODERTXDAC_STMRO_STMRTCSRQDSP6FWSS_CSRQDSP6SWSS_CSRMPSSREGSUSB1_HSPPSSO_DEINTRPUCDMA_EQUNAVQDSP6FWSS_SAWQDSP6SWSS_SAWENC_BURST_FWDEMOD_1XHSDDRXO_TXTQ_ARRAYHAL_SBI_SSBI_V2_NOFTM������Q�Q�����DrDx�nmn�mxs�tXtt�sxLo�}D��u�wDu|v�Po{???ȀT�U07 0000 SHA107 0001 SHA256
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