Monday, February 18, 2013

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D:\workspace\HUDSON_GA_ICECREAM_QUINCY-ATT_CP\modem_proc\core\boot\secboot2\common\shared\src\boot_clobber_prot.c
D:\workspace\HUDSON_GA_ICECREAM_QUINCY-ATT_CP\modem_proc\core\boot\secboot2\common\shared\src\boot_hash_if.c
D:\workspace\HUDSON_GA_ICECREAM_QUINCY-ATT_CP\modem_proc\core\boot\secboot2\common\shared\src\boot_auth_if.c
D:\workspace\HUDSON_GA_ICECREAM_QUINCY-ATT_CP\modem_proc\core\boot\secboot2\common\shared\src\osbl_prog_boot_mproc.c
D:\workspace\HUDSON_GA_ICECREAM_QUINCY-ATT_CP\modem_proc\core\boot\secboot2\common\target\mdm9x00\src\boot_pbl_accessor.c
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FPGA_LED_BITSHIFT HWIO_HAPPY_LED_ADDR FPGA_VERSION MAX_PLATFORMS
WDOG_EN SDIO_BOOT_EN ROM_BOOT_EN UART_BOOT_EN AUX_JTAG_EN ETM_EN
UIM1_EN UIM1_PMIC_EN UART2_DM UART3_DM USB_FS_CTL I2C_EN WLAN_EN
FPGA_PLATFORM FPGA_PLATFORM_CNTR FPGA_PLATFORM_CODES FPGA_PLATFORM_MAP
CHIP_SELECT PlatformInfoTypeOverride PlatformInfoFusedChip EBI2CS2
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DALSBI:
The requested SBI bus conflicts with another SBI bus that has already been
configured! DALSBI: Mismatch detected in the global context version --
drivers on modem and apps don't match! DALSBI: Attempt to open a SBI bus
that failed to properly initialize! DalSBI::SetClientSlaveSettings:
Parameter size doesn't match type DalSBI::SetClientSlaveSettings: NULL
pointer passedBuffer length is zero DALSBI: Bus re-configuration not
allowed for multiproc shared buses DalSBI::GetClientSlaveSettings:
Parameter size doesn't match type DalSBI::Read: Address buffer length
doesn't match data buffer length DalSBI::Write: Address buffer length
doesn't match data buffer length DMOV GetTransferResult: poll a chan
whose domain NOT controlled by local processor Dmov_SetChanOperationMode:
called by %d without opening the handle Dmov_SetChanOperationMode: called
by %s without opening the handle DMOV set chan mode: channel %d can not be
configured to interrupt mode M IJ L K L 5L
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put pending transfer to DONE queue without notification DMOV Request not
Valid: Boot and Tools should allocate their own command list memory DMOV
Stop Handler: hardware channel %d error occured during stop DMOV Read
Result: no active transfers, clock may be off, returning! DMOV Read Result:
result with no pending Transfer on channel %d!

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�: l6 osbl_auth osbl_hash osbl_sahara_if crc.c Assertion byte_ptr
!= NULL failed Assertion buf_ptr != NULL failed Invalid SMEM buffer size
requested for memory %d. Invalid SMEM memory type, %d,
requested. smem.c Invalid memory type %d Out of shared memory have %d
requested %d for %d The smem allocation table is too small Can't initialize
heap info SMEM layout mismatch for %d %x != %x sdioc_init_proc.c Assertion
"Unsupported SDIOC device" == NULL failed Assertion dr == DAL_SUCCESS
failed Copy to smem failed! Sources SMEM init
failed! clkrgm_mpss_boot.c spinlock.c Invalid argument to spin_lock Invalid
argument to spin_unlock clkrgm_sources.c Reconfiguring local active PLL:
%d [clk_regime_is_source_enabled] Source out of range:
%d [clk_regime_is_source_client] Client out of range:
%d [clk_regime_source_request] Client out of range: %d Cannot reconfigure
shared PLL: %d, votes=0x%x Resource %d is exclusive, used by %x
(c=%d) Clock %d released (usage=%d, ext=%d) Clock %d requested (usage=%d,
ext=%d) Client %d released resource %d (clients=%x) Client %d requested
resource %d (clients=%x) clkrgm_rm.c Usage count already zero,
clock=%d Invalid client/resource: c=%d, r=%d Invalid resource: r=%d Need
code changes to support more than 64 clients Unsupported Regime EMDH
Unsupported Regime PMDH Cannot switch adsp clk, not owned by
processor! Unsupported Regime MI2S CODEC RX on this Target! Unsupported
Regime MI2S CODEC TX on this Target! Unsupported Regime vdc on this
Target! Unsupported Regime ecodec on this Target! Unsupported Regime
GP clkrgm_msm.c Unsupported Regime VFE new_src: %d Unsupported Regime SDC1
speed: %d Unsupported Regime UART1 speed: %d Not the Regime Owner UART1
speed: %d Unsupported Regime SDC2 speed: %d Unsupported Regime UART2 speed:
%d Not the Regime Owner UART2 speed: %d Unsupported Regime SDC3 speed:
%d Unsupported Regime UART3 speed: %d Not the Regime Owner UART3 speed:
%d Unsupported Regime SDC4 speed: %d Unsupported Regime UART1DM speed:
%d Invalid VFE source: %d Unsupported GP source: %d Unsupported QDSP6
regime: %d Unsupported Regime vdc perf: %d Unsupported sdac cfg:
%d Unsupported Regime sdac cfg: %d Unsupported sdc cfg: %d Unsupported
ecodec cfg: %d Unsupported Regime ecodec cfg: %d Unsupported icodec_rx cfg:
%d Unsupported Regime icodec_rx cfg: %d Unsupported icodec_tx cfg:
%d Unsupported Regime icodec_tx cfg: %d Invalid GP config: %d Unsupported
clk: %d freq: %d Match: %d Unsupported clk: %d freq: %d match:
%d [clk_regime_msm_off] Unsupported clock: %d [clk_regime_msm_on]
Unsupported clock: %d [clk_regime_msm_reset] Unsupported clock:
%d [clk_regime_msm_reset_assert] Unsupported clock:
%d [clk_regime_msm_reset_deassert] Unsupported clock:
%d [clk_regime_msm_sel_clk_inv] Unsupported clock: %d Clock divider request
for unsupported clock: %d [clk_regime_msm_is_enabled] Invalid clock:
%d [clk_regime_msm_is_supported] Invalid clock: %d [clk_regime_msm_enable]
Invalid clock: %d [clk_regime_msm_disable] Invalid clock:
%d [clk_regime_msm_off] Invalid clock: %d [clk_regime_msm_on] Invalid
clock: %d [clk_regime_msm_is_on] Invalid clock: %d [clk_regime_msm_reset]
Invalid clock: %d [clk_regime_msm_on] Processor not owner of clock:
%d Unsupported ADSP clk: %d Unsupported Regime MI2S CODEC RX new_clk: %d g5
Regime MI2S CODEC TX new_clk: %d Unsupported QDSP6 performance level:
%d Unsupported Regime MDP_LCDC freq: %d Unsupported Regime Camera new_freq:
%d [clk_regime_msm_get_perf_level_freq_khz] Unsupported param: %d %d Unable
to find regime %d in sync list of %d NULL source for clk %d Invalid UARTDM
config: regime=%d, cfg=%d Invalid UART config: clk=%d, cfg=%d Invalid UART:
clk=%d Cannot switch %d clk, not supported Clock %d mux not supported PMIC:
GPIO ENABLE set to HIGH PMIC: End
pm_vreg_set_level_TI_TPS62651_external_smps() call with Range ERROR PMIC:
End pm_vreg_set_level_TI_TPS62651_external_smps() call with SUCCESS PMIC:
GPIO ENABLE set to LOW PMIC: Start
pm_vreg_control_TI_TPS62651_external_smps() call cmd = %d PMIC: Start
pm_vreg_set_level_TI_TPS62651_external_smps() call level = %d, NACK status
= %d PMIC: pm_DalI2C_Read() reg = %x, val = %x, result = %d PMIC: End
pm_vreg_control_TI_TPS62651_external_smps() call PMIC: Before
pm_set_vsel_high_operating_mode() pm_vreg_external_smps_i.c PMIC: setting
VSEL low, threshokd = %d, status = %d PMIC: setting VSEL high, threshold =
%d, status = %d PMIC: pm_DalI2C_Write() reg = %x, val = %x, result =
%d PMIC: End pm_vreg_set_level_TI_TPS62651_external_smps() call with ERROR.
Will use GPIO now PMIC: Could not set SMPS high operating mode. I2C write
error: %x clkrgm_msm_bridge.c Invalid bridge: %d Invalid bridge request:
%d Bridge control for %d tied to clock Unable to switch fabric
clock! clkrgm_fabric.c Unsupported FABRIC perf level:
fabric_clk=%d clkrgm_sdram.c Unsupported SDRAM perf level:
sdram_clk=%d clkrgm_msm_rm.c Invalid resource or clk: r=%d,
clk=%d MDM1000 QST1000 MDM2000 MDM3000 QST1100 MDM6200 MSM7200 MDM8200
MDM9200 QST1500 MSM7500 QST1600 MDM6600 MSM7600 MDM9600 QST1700
MSM7800 MDM8900 MDM6210 MDM6610 MDM8220 MSM7230 MSM7630 ESC6240
QSC6240 QSD8250 QSD8550 QSD8650 QSD8850 APQ8060 MSM6260 MSM8260
MSM8660 ESC6270 QSC6270 MSM6280 ESM6290 MSM6290 MSM7225-1 MSM7625-1
MSM7227-1 MSM7627-1 MSM7201 MSM7601 MSM7625-2 MSM7627-2 QSD8672
QST1005 QST1105 ESM7205 MDM6215 MDM6615 ESM7225 MSM7225 MSM7525
MSM7625 ESM6235 MSM6245 APQ8055 QSC6155 MSM6255 MSM8255 MSM8655
QSC6165 QSC6175 QSC6185 QSC6285 QSC6195 ESC6295 QSC6295 QSC6695
ESM7206 ESM6246 MSM6246 ESM7227 MSM7227 MSM7627 MSM7200A MDM8200A
MSM7500A QSD8250A QSD8650A MSM7201A ESM7205A MSM6255A ESM7206A UNKNOWN
ADMH00 INTCTL0 TXR0 ADMH01 FPB1 SDC1 CLK_CTL_SH1 SPI1 INTCTL1 SDIO1
TLMMGPIO1 TXR1 GEN2AXI_NX1 ADMH02 A2 FPB2 SDC2 CLK_CTL_SH2 SSBI2 SPI2
INTCTL2 SDIO2 EBI2CS2 UART2 GEN2AXI_NX2 ADMH03 FPB3 SDC3 CLK_CTL_SH3
INTCTL3 CRYPTO3 UART3 SDC4 INTCTL4 SDC5 INTCTL5 INTCTL6 INTCTL7 CRA
DFAB PERPH_WEB AHB2AHB QDSP6FWSS_PUB QDSP6SWSS_PUB CWBC GPS_GACC
GNSS_ADC QLIC TOP_FABRIC USB2_HSIC XMEMC QDSP6FWSS_SIRC QDSP6SWSS_SIRC
MPSS_AHB_MISC NTC RFD EBI2ND O_RX_FE DAYTONA_PIPE SPARE SIC_NON_SECURE
TSIF MPSS_MUTEX_REG QDSP6FW_L2TCM_CFG QDSP6SW_L2TCM_CFG TG TLMMGPIO1SH
PEI MPSS_ARM9_MTI WCDMA_DEMBACK SDC1_DML SDC2_DML SDC3_DML SDC4_DML
SDC5_DML MEM_POOL SEC_CTRL MPSS_SEC_INTCTL CHIP_PRI_INTCTL CLK_CTL
SDC1_BAM SDIO1_BAM A2_BAM SDC2_BAM SDIO2_BAM SDC3_BAM SDC4_BAM
SDC5_BAM USB2_HSIC_BAM USB1_HS_BAM IRAM PPSS_CODE_RAM PPSS_BUF_RAM
UART1DM NAV_DM HDEM MODEM MDSPMEM DAYTONA_PMEM QDSP6FWSS_IM
QDSP6SWSS_IM BPM A9_MPM EBI2XM MPSS_TIMERS_MICRO MPSS_TIMERS_SLP EVP
EBI2CR DECODER TXDAC_STMR O_STMR TCSR QDSP6FWSS_CSR QDSP6SWSS_CSR
MPSSREGS USB1_HS PPSS O_DEINT RPU CDMA_EQU NAV QDSP6FWSS_SAW
QDSP6SWSS_SAW ENC_BURST_FW DEMOD_1X HSDDRX O_TX TQ_ARRAY
HAL_SBI_SSBI_V2_NOFTM � ���� �Q �Q �� � �� Dr Dx
�n m n �m xs �t Xt t �s x Lo �} D� �u �w Du
|v � Po { ???
Ȁ T�

U
07 0000 SHA1 07 0001 SHA256

- Format: Log Type - Time(microsec) - Message Log type: B - since
boot(excluding boot rom). D - delta
OVERFLOW � �S � h$ t$ \$ 4% �$ �% @% �% �S

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